1. Technical Field
The present disclosure relates generally to semiconductor memories and, more particularly, to a vertical trench memory cell having an insulating ring.
2. Description of Related Art
Trench memory with a vertical transistor and a trench capacitor has been widely developed to provide an alternative path to scale the sizes of memory cells. For example, a dynamic random access memory (DRAM) is a capacitor for storing charge and a pass transistor (also called a pass gate or access transistor) for transferring charge to and from the capacitor. Data (i.e. 1 bit) stored in the cell is determined by the absence or presence of charge on the storage capacitor. As the minimum feature size of vertical DRAM arrays is scaled, cell-to-cell interaction becomes an increasing concern. Moreover, because cell size determines chip density, size and cost, reducing cell area is one of the DRAM's designer's primary goals. Typically, reducing cell area is done by reducing features size to shrink the cell.
Besides shrinking the cell features, the most effective means to reduce the cell area is to reduce the largest feature in the cell, typically, the area of the storage capacitor. However, shrinking the capacitor plate area reduces capacitance and, consequently, reduces stored charge. Reduced charge means that whatever charge is stored in the DRAM is more susceptible to noise, soft errors, leakage and other well known DRAM problems. Thus another primary goal for DRAM cell designers is to maintain storage capacitance while reducing cell area.
FIG. 1 illustrates a cross-sectional view of a conventional vertical transistor memory 10, which includes a trench capacitor 15 and vertical transistor 17. Trench capacitor 15 includes a first capacitor electrode 12 (e.g. a buried plate including a doped region in a substrate), a second capacitor electrode 13 (e.g. doped polysilicon inside the trench capacitor), and a node dielectric 14 (e.g. oxide, nitride and/or a high-k material). Vertical transistor 17 includes a gate electrode 23 (e.g. doped polysilicon inside the trench), a gate dielectric 22 (e.g. oxide) positioned on a trench sidewall, a first source/drain terminal 21 and a second source/drain terminal 28 (e.g. a doped outdiffusion regions 28a, 28b, 28c and 28d formed by diffusion of dopants from capacitor electrode 13 through a buried strap 18 (e.g. polysilicon)). Capacitor electrode 13 and gate electrode 23 are electrically insulated by a trench top oxide (TTO) insulator 20. Buried strap 18 and buried plate 12 are electrically insulated by a collar 16 (e.g. oxide). Transistor memory 10 includes an array of memory cells interconnected by bitlines or rows 24 and wordlines or columns 26. Strap outdiffusion regions 28a, 28b, 28c and 28d are formed by driving dopants in capacitor electrode 13 to diffuse through buried strap 18 during thermal processes.
When vertical transistor trench memory is used in an electrical circuit, it is usually desired to have each individual memory cell electrically isolated. However, as semiconductor device scales, vertical transistor memory is susceptible to the issue of merging buried strap outdiffusion (BSOD) of neighboring cells. For example, as illustrated in FIG. 1, strap outdiffusion region 28c of the memory cell on the left undesirably overlaps with strap outdiffusion region 28b of the memory cell on the right (indicated by reference numeral 30), resulting in electrical short of these two cells. As device feature sizes scale downward, the space between two neighboring trenches is reduced, thus aggravating the merging of strap outdiffusion regions 28b and 28c, as illustrated by the figure.
Accordingly, a need exists for forming vertical trench memory cell using alternative methods circumventing the limitations of downward scaling. The present disclosure provides a structure and method of forming a vertical transistor trench memory cell unreceptive to BSOD merging.